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MSM9201-xx 1/34 ? semiconductor general description the MSM9201-xx is a dot matrix fluorescent display tube controller driver ic which displays characters, numerics and symbols. dot matrix fluorescent display tube drive signals are generated by serial data sent from a micro- controller. a display system is easily realized by internal rom and ram for character display. the MSM9201-xx has low power consumption since it is made by cmos process technology. -01 is available as a general code. custom codes are provided on customer's request. features ? logic power supply (v dd ) : 3.3 v 10%/5.0 v 10% ? fluorescent display tube drive power supply (v disp ) : 3.3 v 10%/5.0 v 10% ? fluorescent display tube drive power supply (v fl ) : C20 to C60 v ? vfd driver output current (vfd driver output can directly be connected to the fluorescent display tube. no pull-down resistor is required.) - segment driver (seg1 to seg35) : C5.0 ma (v fl =C60v) - segment driver (ad1 to ad8) : C10.0 ma (v fl =C60v) - grid driver (com1 to com16) : C20.0 ma (v fl =C60v) ? general output port output current - output driver (p1-4) : 1.0 ma (v dd =3.3v 10%) 2.0 ma (v dd =5.0v 10%) ? content of display - cgrom 5 7 dots, 240 types (character data) - cgram 5 7 dots, 16 types (character data) - adram 24 (display digit) 4 bits (symbol data) - dcram 24 (display digit) 8 bits (register for character data display) - general output port 4 bits (static mode) ? display control function - display digit : 9 to 24 digits - display duty (contrast adjustment) : 8 stages - all lights on/off ? 3 interfaces with microcontroller : da, cs , cp (4 interfaces if reset is added) ? 1-byte instruction execution (excluding data write to ram) ? built-in oscillation circuit (external c and r) ? package options: 80-pin plastic qfp (qfp80-p-1414-0.65-k) (product name: MSM9201-xxgs-k) 80-pin plastic qfp (qfp80-p-1420-0.80-bk) (product name: MSM9201-xxgs-bk) xx indicates the code number. preliminary ? semiconductor MSM9201-xx fluorescent display tube controller driver e2c0039-27-y2 this version: nov. 1997 previous version: jul. 1996
MSM9201-xx 2/34 ? semiconductor block diagram v disp v dd gnd v fl reset da cp cs osc0 osc1 seg1 seg35 ad1 ad4 p1 p4 com1 com24 dcram 24w 8b cgrom 240w 35b cgram 16w 35b adram 24w 8b 8-bit shift register command decoder control circuit timing generator 1 oscillator timing generator 2 digit control duty control grid driver port driver ad driver segment driver dcram address counter write address counter read address counter address selector
MSM9201-xx 3/34 ? semiconductor input and output configuration schematic diagrams of logic portion input and output circuits input pin v dd v dd input gnd gnd output pin schematic diagram of driver output circuit v disp output v fl v fl v disp v dd output v dd gnd gnd
MSM9201-xx 4/34 ? semiconductor pin configuration (top view) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 ad2 ad1 v disp2 nc v fl2 p4 p3 p2 p1 v dd da cp cs reset osc1 osc0 gnd v fl1 com24 com23 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32 seg33 seg34 seg35 v disp1 com1 com2 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 com22 com21 com20 com19 com18 com17 com16 com15 com14 com13 com12 com11 com10 com9 com8 com7 com6 com5 com4 com3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 ad3 ad4 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 nc: no connection 80-pin plastic qfp (qfp80-p-1414-0.65-k)
MSM9201-xx 5/34 ? semiconductor com1 41 com2 42 com3 43 com4 44 com5 45 com6 46 com7 47 com8 48 com9 49 com10 50 com11 51 com12 52 com13 53 com14 54 com15 55 com16 56 com17 57 com18 58 com19 59 com20 60 com21 61 com22 62 com23 63 com24 64 v disp1 40 seg35 39 seg34 38 seg33 37 seg32 36 seg31 35 seg30 34 seg29 33 seg28 32 seg27 31 seg26 30 seg25 29 seg24 28 seg23 27 seg22 26 seg21 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 seg20 seg19 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 ad4 ad3 ad2 ad1 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 v fl1 gnd osc0 osc1 reset cs cp d4 v dd p1 p2 p3 p4 v fl2 nc v disp2 nc: no connection 80-pin plastic qfp (qfp80-p-1420-0.80-bk)
MSM9201-xx 6/34 ? semiconductor pin descriptions qfp -2* symbol type description 5-39 seg1-35 o fluorescent tube anode electrode 41-64 com1-24 o fluorescent tube grid electrode 1-4 ad1-4 o fluorescent tube anode electrode 74-77 p1-4 o led drive control terminals general port output. output of these pins in static operation, so these pins can drive the led. i oh >C2.0 ma 73 v dd 40, 80 v disp1-2 66 gnd 65, 78 v fl1-2 power supply fluorescent display tube anode electrode drive output. directly connected to fluorescent display tube. no pull-down resistor is required. i oh >C5.0 ma fluorescent display tube grid electrode drive output. directly connected to fluorescent display tube. no pull-down resistor is required. i oh >C20.0 ma fluorescent display tube anode electrode drive output. directly connected to fluorescent display tube. no pull-down resistor is required. i oh >C10.0 ma v dd -gnd are power supplies for internal logic. v disp -v fl are power supplies for driving fluorescent tubes. use the same power supply for v dd and v disp . connects to: 72 da i micro- controller serial data input (positive logic). input from lsb. 71 cp i micro- controller shift clock input. serial data is shifted on the rising edge of cp . 70 cs i micro- controller chip select input. setting this pin to "h" disables serial data transfer. qfp -1* 3-27 39-62 1, 2, 79, 80 72-75 71 38, 78 64 63, 76 70 69 68 pin * qfp-1 : qfp80-p-1414-0.65-k qfp-2 : qfp80-p-1420-0.80-bk
MSM9201-xx 7/34 ? semiconductor pin symbol type description 65 osc0 i c 1 , r 1 66 osc1 o external rc pin for rc oscillation. connect r and c externally. the rc time constant depends on the v dd voltage used. set the target oscillation frequency to 2 mhz. connects to: osc0 osc1 r 1 c 1 67 reset i micro- controller reset input. setting this pin to "low" initializes all the functions. the initial status is as follows. ? address of each ram ? data of each ram ? number of display digits ? contrast adjusment ? all lights on or off ? all outputs address "00"h content is undefined 24 digits 8/16 off mode "low" level reset r 2 c 2 (circuit when r and c are connected externally) see application circuit. (rc oscillation circuit) see application circuit. or c 2 , r 2 qfp -2* qfp -1* 67 68 69 * qfp-1 : qfp80-p-1414-0.65-k qfp-2 : qfp80-p-1420-0.80-bk
MSM9201-xx 8/34 ? semiconductor absolute maximum ratings parameter supply voltage 1 symbol condition rating unit supply voltage 2 input voltage power dissipation storage temperature output current v dd v disp v fl v in p d t stg i o3 (*1) ta 25c com1-com24 ad1-ad4 seg1-seg35 C0.3 to +6.5 C80 to v disp +0.3 C80 to v dd +0.3 qfp80-p-1414-0.65-k C55 to +150 C10 to 0.0 v v v mw c C30 to 0.0 C20 to 0.0 ma i o1 i o2 (*1) C0.3 to +6.5 v i o4 p1-p4 C4.0 to +4.0 qfp80-p-1420-0.80-bk 565 643 *1 use the same power supply for v dd and v disp . recommended operating conditions (1) when the power supply voltage is 5v (typ) parameter supply voltage 1 symbol condition min. typ. max. unit supply voltage 2 high level input voltage low level input voltage cp frequency oscillation frequency frame frequency operating temperature v dd v disp v fl v ih v il f c t op all input pins excluding osc0 pin all input pins excluding osc0 pin r=3.3k w , c=47pf digit=1-24, r=3.3k w , c=47pf 4.5 C60 0.7v dd C40 5.0 5.5 C20 0.3v dd 1.0 85 v v v v mhz c 1.5 122 2.0 163 2.5 204 mhz hz f osc f fr recommended operating conditions (2) when the power supply voltage is 3.3v (typ) parameter supply voltage 1 symbol condition min. typ. max. unit supply voltage 2 high level input voltage low level input voltage cp frequency oscillation frequency frame frequency operating temperature v dd v disp v fl v ih v il f c t op all input pins excluding osc0 pin all input pins excluding osc0 pin r=3.3k w , c=39pf digit=1C24, r=3.3k w , c=39pf 3.0 C60 0.8v dd C40 3.3 3.6 C20 0.2v dd 1.0 85 v v v v mhz c 1.5 122 2.0 163 2.5 204 mhz hz f osc f fr
MSM9201-xx 9/34 ? semiconductor electrical characteristics dc characteristics (1) parameter symbol applied pin condition min. max. unit high level input voltage v ih cs , cp , da, reset cs , cp , da, reset da, reset low level input voltage v ih =v dd v il =0.0v cs , cp , da, reset v il i ih i il high level input current low level input current high level output voltage v oh1 v oh2 v oh3 v oh4 com1-24 ad1-4 seg1-35 p1-4 i dd1 p1-4 com1-24 ad1-4 seg1-35 v dd , v disp i oh1 =C20.0ma i oh2 =C10.0ma i oh3 =C5.0ma i oh4 =C2.0ma duty=15/16 digit=1C24 all outputs go on low level output voltage supply current 0.7v dd C1.0 C1.0 v disp C1.5 v disp C1.5 v disp C1.5 v dd C1.0 0.3v dd 1.0 1.0 1.0 4 3 v v a a v v v v v ma ma (v dd =v disp =5.0v10%, v fl =C60v, ta=C40 to +85c, unless otherwise specified) cs , cp , v fl +1.0 v i ol1 =2ma v ol2 v ol1 i dd2 f osc = 2mhz, no load duty=8/16 digit=1C9 all outputs go off
MSM9201-xx 10/34 ? semiconductor dc characteristics (2) parameter symbol applied pin condition min. max. unit high level input voltage v ih cs , cp , da, reset cs , cp , da, reset da, reset low level input voltage v ih =v dd v il =0.0v cs , cp , da, reset v il i ih i il high level input current low level input current high level output voltage v oh1 v oh2 v oh3 v oh4 com1-24 ad1-4 seg1-35 p1-4 i dd1 p1-4 com1-24 ad1-4 seg1-35 v dd , v disp i oh1 =C20.0ma i oh2 =C10.0ma i oh3 =C5.0ma i oh4 =C1.0ma duty=15/16 digit=1C24 all outputs go on low level output voltage supply current 0.8v dd C1.0 C1.0 v disp C1.5 v disp C1.5 v disp C1.5 v dd C1.0 0.2v dd 1.0 1.0 1.0 3 2 v v a a v v v v v ma ma (v dd =v disp =3.3v10%, v fl =C60v, ta=C40 to +85c, unless otherwise specified) cs , cp , v fl +1.0 v i ol1 =2ma v ol2 v ol1 i dd2 f osc = 2mhz, no load duty=8/16 digit=1C9 all outputs go off
MSM9201-xx 11/34 ? semiconductor ac characteristics (1) ac characteristics (2) parameter symbol condition min. max. unit cp pulse width da setup time da hold time cs setup time cs hold time cs wait time data processing time reset pulse width da wait time slew rate (all drivers) v dd rise time t cw t ds t dh t css t csh t csw t doff t wres t rsoff t r t prz r 1 =3.3k w , c 1 =39pf r 1 =3.3k w , c 1 =39pf c l =100pf when mounted on the unit 300 300 300 300 16 300 8 300 4.0 100 ns ns ns ns m s ns m s m s m s m s cp frequncy f c 1.0 mhz when reset signal is input externally 300 ns (v dd , v disp =3.3v10%, v fl =C60v, ta=C40 to +85c, unless otherwise specified) t f 4.0 m s t r =20% to 80% t f =80% to 20% v dd off time t pof when mounted on the unit, v dd =0.0v 5.0 ms parameter symbol condition min. max. unit cp pulse width da setup time da hold time cs setup time cs hold time cs wait time data processing time reset pulse width da wait time slew rate (all drivers) v dd rise time t cw t ds t dh t css t csh t csw t doff t wres t rsoff t r t prz r 1 =3.3k w , c 1 =47pf r 1 =3.3k w , c 1 =47pf t r =20% to 80% t f =80% to 20% when mounted on the unit 300 300 300 300 16 300 8 300 4.0 100 ns ns ns ns m s ns m s m s m s m s cp frequncy f c 1.0 mhz when reset signal is input externally 300 ns (v dd , v disp =5.0v10%, v fl =C60v, ta=C40 to +85c, unless otherwise specified) t f c l =100pf 4.0 m s v dd off time t pof when mounted on the unit, v dd =0.0v 5.0 ms
MSM9201-xx 12/34 ? semiconductor timing diagram symbol v ih v il v dd =3.3v10% 0.8 v dd 0.2 v dd v dd =5.0v10% 0.7 v dd 0.3 v dd ? data timing cs cp da t css f c t ds t dh t doff t cw t cw t csh t csw valid valid valid valid 0.7 v dd v ih 0.3 v dd v il v ih v il ? reset timing ? output timing v dd reset da t prz t rson t rsoff t wres when external r and c are connected. when input externally 0.8 v dd v ih 0.0 v v il v ih v il all outputs t f t r 0.8 v disp 0.2 v fl
MSM9201-xx 13/34 ? semiconductor digit output timing (for 24-digit display, at a duty of 15/16) com1 com2 com3 com4 com5 com6 v fl t 1 =1536t t 2 =60t t 3 =4t frame cycle display timing blank timing v disp v fl v disp t=8/ f osc (t 1 =6.144 ms when f osc =2.0 mhz) (t 2 =240 m s when f osc =2.0 mhz) (t 3 =16 m s when f osc =2.0 mhz) com19 com20 com21 com22 com23 com24 ad1-4 seg1-35
MSM9201-xx 14/34 ? semiconductor functional description command list 1st byte 2nd byte lsb msb lsb msb command 1 dcram data write b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 2 3 4 5 6 7 cgram data write 1 adram data write general output port set display duty set number of display digits set all lights on/off test mode c0 c1 c2 c3 c4 c5 c6 c7 c0 c5 c10 c15 c20 c25 c30 * c1 c6 c11 c16 c21 c26 c31 * c2 c7 c12 c17 c22 c27 c32 * c3 c8 c13 c18 c23 c28 c33 * c4 c9 c14 c19 c24 c29 c34 * c0 c1 c2 c3 **** x0 x1 x2 x3 x4 1 0 0 x0 x1 x2 x3 * 010 x0 x1 x2 x3 x4 1 1 0 p1 p2 p3 p4 * 001 d0 d1 d2 ** 101 k0 k1 k2 k3 * 011 lh *** 111 2nd byte 3rd byte 4th byte 5th byte 6th byte * xn cn pn dn kn h l : don't care : address specification for each ram : character code specification for each ram : general output port status specification : display duty specification : number of display digits specification : all lights on instruction : all lights off instruction note: the test mode is used for inspection before shipment. it is not a user function. when data is written to ram (dcram, cgram, adram) continuously, addresses are internally incremented automatically. therefore it is not necessary to specify the 1st byte when ram data for the 2nd and later bytes is written.
MSM9201-xx 15/34 ? semiconductor positional relationship between segn and adn (one digit) c0 ad1 c0 seg1 c5 seg6 c10 seg11 c15 seg16 c20 seg21 c25 seg26 c30 seg31 c1 seg2 c6 seg7 c11 seg12 c16 seg17 c21 seg22 c26 seg27 c31 seg32 c2 seg3 c7 seg8 c12 seg13 c17 seg18 c22 seg23 c27 seg28 c32 seg33 c3 seg4 c8 seg9 c13 seg14 c18 seg19 c23 seg24 c28 seg29 c33 seg34 c4 seg5 c9 seg10 c14 seg15 c19 seg20 c24 seg25 c29 seg30 c34 seg35 adram written data. corresponds to 2nd byte cgram data write mode. corresponds to 2nd byte cgram data write mode. corresponds to 3rd byte cgram data write mode. corresponds to 4th byte cgram data write mode. corresponds to 6th byte cgram data write mode. corresponds to 5th byte c1 ad2 c2 ad3 c3 ad4
MSM9201-xx 16/34 ? semiconductor data transfer method and command write method display control command and data are written by an 8-bit serial transfer. write timing is shown in the figure below. setting the cs pin to "low" level enables a data transfer. data is 8 bits and is sequentially input into the da pin from lsb (lsb first). as shown in the figure below, data is read by the shift register at the rise of the shift clock, which is input into the cp pin. if 8-bit data is input, internal load signals are automatically generated and data is written to each register and ram. therefore it is not necessary to input load signals from the outside. setting the cs pin to "high" disables data transfer. data input from the point when the cs pin changes from "high" to "low" is recognized in 8-bit units. * when data is written to ram (dcram, adram, cgram) continuously, addresses are internally incremented automatically. therefore it is not necessary to specify the 1st byte to write ram data for the 2nd and later bytes. reset function reset is executed when the reset pin is set to "l", (when turning power on, for example,) which initializes all functions. the initial status is as follows. ? address of each ram .................. address "00"h ? data of each ram ........................ all contents are undefined ? general output port ..................... all general output ports go "low" ? number of display digits ............ 24 digits ? contrast adjustment ..................... 8/16 ? all display lights on or off ..... off mode ? segment output ............................ all segment outputs go "low" ? ad output ..................................... all ad outputs go "low" after reset is executed, perform settings again according to "initial setting flowchart" shown later. t doff b0 lsb cs cp da b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 msb 1st byte lsb msb 2nd byte when data is written to dcram* command and address data t csh b0 b1 b2 b3 b4 b5 b6 b7 lsb msb 2nd byte character code data of the next address character code data
MSM9201-xx 17/34 ? semiconductor description of commands and functions 1. dcram data write (specifies the address (00h to 1fh) of dcram and writes the character code of cgrom and cgram.) dcram (data control ram) has 5-bit addresses to store character code of cgrom and cgram. the character code specified in dcram is converted to a 5 7 dot matrix character pattern via cgrom or cgram. the dcram can store 24 characters. [command format] x0 x1 x2 x3 x4 1 0 0 b0 b1 b2 b3 b4 b5 b6 b7 1st byte (1st) lsb msb c0 c1 c2 c3 c4 c5 c6 c7 b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (2nd) lsb msb : selects dcram data write mode and specifies dcram address. (ex: specifies dcram address 00h) : specifies character code of cgrom and cgram. ( written into dcram address 00h ) to specify the character code of cgrom and cgram continuously to the next address, specify only character codes as follows. since the addresses of dcram are automatically incremented, they do not need to be specified.
MSM9201-xx 18/34 ? semiconductor c0 c1 c2 c3 c4 c5 c6 c7 b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (3rd) lsb msb c0 c1 c2 c3 c4 c5 c6 c7 b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (4th) lsb msb : specifies character code of cgrom and cgram. (written into dcram address 01h) : specifies character code of cgrom and cgram. (written into dcram address 02h) b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (25th) lsb msb c0 c1 c2 c3 c4 c5 c6 c7 b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (26th) lsb msb : specifies character code of cgrom and cgram. (written into dcram address 17h) : specifies dummy character code of cgrom and cgram. (not written into dcram address) b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (33th) lsb msb c0 c1 c2 c3 c4 c5 c6 c7 b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (34th) lsb msb : specifies dummy character code of cgrom and cgram. (not written into dcram address) : specifies character code of cgrom and cgram. (rewritten into dcram address 00h) c0 c1 c2 c3 c4 c5 c6 c7 c0 c1 c2 c3 c4 c5 c6 c7 x0 (lsb) to x4 (msb): dcram address (5 bits: 24 characters) c0 (lsb) to c7 (msb): character code of cgrom and cgram (8 bits: 256 characters) setting of cgrom and cgram character codes for up to 24 digits is now complete. to further specify character codes continuously from dcram address 00h, dummy character codes must be specified for dcram address 18h to 1fh (so that dcram address will be incremented automatically and will be reset to 00h).
MSM9201-xx 19/34 ? semiconductor [com positions and set dcram address] hex com position x0 x1 x2 x3 x4 hex com position x0 x1 x2 x3 x4 00 com1 00000 10 com17 00001 01 com2 10000 11 com18 10001 02 com3 01000 12 com19 01001 03 com4 11000 13 com20 11001 04 com5 00100 14 com21 00101 05 com6 10100 15 com22 10101 06 com7 01100 16 com23 01101 07 com8 11100 17 com24 11101 08 com9 00010 18 00011 09 com10 10010 19 10011 0a com11 01010 1a 01011 0b com12 11010 1b 11011 0c com13 00110 1c 00111 0d com14 10110 1d 10111 0e com15 01110 1e 01111 0f com16 11110 1f 11111
MSM9201-xx 20/34 ? semiconductor 2. cgram data write (specifies the addresses 00h to 0fh of cgram and writes character pattern data.) cgram (character generator ram) has 4-bit addresses to store 5 7 dot matrix character patterns. a character pattern stored in cgram can be displayed by specifying the character code (address) in dcram. the addresses of cgram are assigned to 00h to 0fh. (all the other addresses are the cgrom addresses.) (the cgram can store 16 types of character patterns.) [command format] c0 c5 c10 c15 c20 c25 c30 * b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (2nd) lsb msb : specifies 1st column data. (written into cgram address 00h) c1 c6 c11 c16 c21 c26 c31 * b0 b1 b2 b3 b4 b5 b6 b7 3rd byte (3rd) lsb msb : specifies 2nd column data. (written into cgram address 00h) x0 x1 x2 x3 * 010 b0 b1 b2 b3 b4 b5 b6 b7 1st byte (1st) lsb msb : selects cgram data write mode and specifies cgram address. (ex: specifies cgram address 00h) c2 c7 c12 c17 c22 c27 c32 * b0 b1 b2 b3 b4 b5 b6 b7 4th byte (4th) lsb msb : specifies 3rd column data. (written into cgram address 00h) c3 c8 c13 c18 c23 c28 c33 * b0 b1 b2 b3 b4 b5 b6 b7 5th byte (5th) lsb msb : specifies 4th column data. (written into cgram address 00h) c4 c9 c14 c19 c24 c29 c34 * b0 b1 b2 b3 b4 b5 b6 b7 6th byte (6th) lsb msb : specifies 5th column data. (written into cgram address 00h) to specify character pattern data continuously to the next address, specify only character pattern data as follows. since the addresses of cgram are automatically incremented, they do not need to be specified. the 2nd to 6th byte (character pattern data) are regarded as one data item, so 300 ns is sufficient for t doff time between bytes.
MSM9201-xx 21/34 ? semiconductor x0 (lsb) to x3 (msb): cgram address (4 bits: 16 characters) c0 (lsb) to c34 (msb): character pattern data (35 bits: 35 outputs per digit) c0 c5 c10 c15 c20 c25 c30 * b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (7th) lsb msb : specifies 1st column data. (written into cgram address 01h) c4 c9 c14 c19 c24 c29 c34 * b0 b1 b2 b3 b4 b5 b6 b7 6th byte (11th) lsb msb : specifies 5th column data. (written into cgram address 01h) c0 c5 c10 c15 c20 c25 c30 * b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (12th) lsb msb : specifies 1st column data. (written into cgram address 02h) c4 c9 c14 c19 c24 c29 c34 * b0 b1 b2 b3 b4 b5 b6 b7 6th byte (16th) lsb msb : specifies 5th column data. (written into cgram address 02h) c0 c5 c10 c15 c20 c25 c30 * b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (77th) lsb msb : specifies 1st column data. (written into cgram address 0fh) c4 c9 c14 c19 c24 c29 c34 * b0 b1 b2 b3 b4 b5 b6 b7 6th byte (81th) lsb msb : specifies 5th column data. (written into cgram address 0fh) c0 c5 c10 c15 c20 c25 c30 * b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (82th) lsb msb : specifies 1st column data. (rewritten into cgram address 00h.) c4 c9 c14 c19 c24 c29 c34 * b0 b1 b2 b3 b4 b5 b6 b7 6th byte (86th) lsb msb : specifies 5th column data. ( rewritten into cgram address 00h. )
MSM9201-xx 22/34 ? semiconductor [cgrom addresses and set cgram addresses] refer to rom code hex x0 cgrom address x1 x2 x3 hex x0 cgrom address x1 x2 x3 00 0000 08 0000 ram00(00000000b) 01 1000 09 1000 ram01(00000001b) ram08(00001000b) ram09(00001001b) 02 0100 0a 0100 ram02(00000010b) 03 1100 0b 1100 ram03(00000011b) ram0a(00001010b) ram0b(00001011b) 04 0010 0c 0010 ram04(00000100b) 05 1010 0d 1010 ram05(00000101b) ram0c(00001100b) ram0d(00001101b) 06 0110 0e 0110 ram06(00000110b) 07 1110 0f 1110 ram07(00000111b) ram0e(00001110b) ram0f(00001111b)
MSM9201-xx 23/34 ? semiconductor positional relationship between the output area of cgrom and that of cgram note: cgrom (character generator rom) has 8-bit addresses to generate 5 7 dot matrix character patterns. cgram can store 240 types opf character patterns. general-purpose code-01 is available and custom codes are provided on customer's request. c0 c5 c10 c15 c20 c25 c30 c1 c6 c11 c16 c21 c26 c31 c2 c7 c12 c17 c22 c27 c32 c3 c8 c13 c18 c23 c28 c33 c4 c9 c14 c19 c24 c29 c34 corresponds to 2nd byte (1st column) corresponds to 3rd byte (2nd column) corresponds to 5th byte (4th column) corresponds to 6th byte (5th column) corres p onds to 4th b y te ( 3rd column )
MSM9201-xx 24/34 ? semiconductor 3. adram data write (specifies address of adram and writes symbol data) adram (additional data ram) has 4-bit addresses to store symbol data. symbol data specified in adram is directly output without cgrom and cgram. (the dram can store 4 types of symbol patterns for each digit.) the terminal to which the contents of adram are output can be used as a cursor. [command format] c0c1c2c3**** b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (2nd) lsb msb : specifies symbol data. ( written into adram address 00h ) x0 x1 x2 x3 x4 1 1 0 b0 b1 b2 b3 b4 b5 b6 b7 1st byte (1st) lsb msb : selects adram data write mode and specifies adram address. (ex: specifies adram address 00h) to specify symbol data continuously to the next address, specify only symbol data as follows. the addresses of adram are automatically incremented. specification of adram addresses is therefore unnecessary. c0c1c2c3**** b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (3rd) lsb msb : specifies symbol data. (written into adram address 01h) c0c1c2c3**** b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (4th) lsb msb : specifies symbol data. (written into adram address 02h) c0c1c2c3**** b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (17th) lsb msb : specifies symbol data. (written into adram address 17fh) c0c1c2c3**** b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (18th) lsb msb : specifies dummy symbol data. (not written into adram address) c0c1c2c3**** b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (65th) lsb msb : specifies dummy symbol data. (not written into adram address) c0 c1 c2 c3 c4 c5 c6 c7 b0 b1 b2 b3 b4 b5 b6 b7 2nd byte (66th) lsb msb : specifies symbol data. (rewritten into adram address 00h.) setting of symbol data for up to 24 digits is now complete. to further specify symbol data continuously from dcram address 00h, dummy symbol data must be specified for adram addresses 18h to 1fh (so that the adram address will be incremented automatically and will be reset to 00h). x0 (lsb) to x4 (msb): adram addresses (5 bits: 24 characters) c0 (lsb) to c3 (msb): symbol data (4 bits: 4-symbol data per digit)
MSM9201-xx 25/34 ? semiconductor [com positions and adram addresses] hex x0 com position x1 x2 x3 hex x0 com position x1 x2 x3 00 0000 10 0000 com1 com17 01 1000 11 1000 com2 com18 02 0100 12 0100 com3 com19 03 1100 13 1100 com4 com20 04 0010 14 0010 com5 com21 05 1010 15 1010 com6 com22 06 0110 16 0110 com7 com23 07 1110 17 1110 com8 com24 08 0001 18 0001 com9 09 1001 19 1001 com10 0a 0101 1a 0101 com11 0b 1101 1b 1101 com12 0c 0011 1c 0011 com13 0d 1011 1d 1011 com14 0e 0111 1e 0111 com15 0f 1111 1f 1111 com16 x4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4. general output port set (specifies the general output port status) the general output port is an output for 4-bit static operation. it is used to control other i/o devices and turn on led. (static operation.) the fluorescent display tube cannot be driven by this output port, because when at the "high" level this output becomes the v dd voltage and when at the "low" level it becomes the ground potential. [command format] p1p2p3p4*001 b0 b1 b2 b3 b4 b5 b6 b7 1st byte lsb msb : selects general output port and specifies the out p ut status. p1-p4 : general output ports * : don't care [set data and set state of general output port] pn 0 1 display state of general output port sets p1-p4 to low sets p1-p4 to high (the state when power is applied or when reset is input)
MSM9201-xx 26/34 ? semiconductor 5. display duty set (writes display duty value to duty cycle register) display duty adjusts contrast in 8 stages using 3-bit data. at the time power is turned on or the reset signal is input, the duty cycle register value is "0". always execute this instruction before turning the display on, then set a desired duty value. [command format] d0d1d2**101 b0 b1 b2 b3 b4 b5 b6 b7 1st byte lsb msb : selects display duty set mode and sets duty value. d0 (lsb) to d2 (msb) : display duty data (3 bits: 8 stages) * : don't care [relation between setup data and controlled com duty] hex d2 d1 d0 com duty 0 0 0 0 8/16 1 0 0 1 9/16 2 0 1 0 10/16 3 0 1 1 11/16 4 1 0 0 12/16 5 1 0 1 13/16 6 1 1 0 14/16 7 1 1 1 15/16 (the state at the time power is turned on or reset signal is input)
MSM9201-xx 27/34 ? semiconductor 6. number of display digits set (writes the number of display digits to the display digit register) the number of display digits set can display 9 to 24 digits using 4-bit data. at the time power is turned on or a reset signal is input, the display digit register value is "0". always execute this instruction to change the number of digits before turning the dispaly on. [command format] k0k1k2k3*011 b0 b1 b2 b3 b4 b5 b6 b7 1st byte lsb msb : selects the number of display digits set mode and specifies the number of digits value. k0 (lsb) to k3 (msb): number of display digits data (4 bits: 16 digits) [relation between setup data and controlled com] the state at the time power is turned on or reset signal is input hex k0 k1 k2 k3 number of digits of com 0 0000 com1-24 1 1000 com1-9 2 0100 com1-10 3 1100 com1-11 4 0010 com1-12 5 1010 com1-13 6 0110 com1-14 7 1110 com1-15 hex k0 k1 k2 k3 number of digits of com 8 0001 9 1001 a 0101 b 1101 c 0011 d 1011 e 0111 f 1111 com1-16 com1-17 com1-18 com1-19 com1-20 com1-21 com1-22 com1-23
MSM9201-xx 28/34 ? semiconductor 7. all display lights on/off set (turns all display lights on or off) the all display lights on mode is used primarily for display testing. the all display lights off mode is primarily used to prevent malfunction on power-up. [command format] lh *** 111 b0 b1 b2 b3 b4 b5 b6 b7 1st byte lsb msb : selects all display lights on or off mode. [set data and display state of seg and ad] h 0 0 1 1 all outputs maintain current states sets all outputs to low sets all outputs to high sets all outputs to high display state of seg and ad l 0 1 0 1 (the state at the time power is applied or reset is input) (all lights on mode has priority.)
MSM9201-xx 29/34 ? semiconductor initial setting flowchart all display lights off specify display duty cgram data write mode (with address set) cgram character code cgram is character code write ended? another ram to be set? release all display lights off mode adram data write mode (with address set) adram character code adram is character code write ended? dcram data write mode (with address set) dcram character code dcram is character code write ended? select a ram to be used status of all outputs by reset signal input normal operation status (display on) address is automatically incremented no no no yes yes yes yes end address is automatically incremented address is automatically incremented start power is applied or reset is input apply v dd apply v fl no specify number of display digits specify general output port status
MSM9201-xx 30/34 ? semiconductor application circuit notes: 1. the v dd value depends on the power supply voltage of the microcontroller used. adjust the values of the constants r 1 , r 2 , r 4 , c 1 , and c 2 to the power supply voltage used. 2. the v fl value depends on the fluorescent display tube used. adjust the values of the constants r 3 and zd to the power supply voltage used. MSM9201-xx micro- controller 24 35 4 reset v dd , v disp1-2 com1-24 seg1-35 ad1-4 v dd gnd r 2 c 2 gnd r 1 c 1 v fl1-2 osc0 osc1 da cp cs output port p1-2 r 3 c 3 c 4 v dd v fl zd 4 5 7-dot matrix fluorescent display tube grid (digit) anode (segment) anode (segment) heater transformer r 4 led v dd npn tr gnd gnd gnd v dd
MSM9201-xx 31/34 ? semiconductor reference data the figure below shows the relationship between the v fl voltage and the output current of each driver. take care that the total power consumption to be used does not exceed the power dissipation. C30 C25 C20 C15 C10 C5 0 C10 C20 C30 C40 C50 C60 output current (ma) v fl voltage (v dd-n ) com1 to com24 (condition: v oh =v disp C1.5 v) ad1 to ad4 (condition: v oh =v disp C1.5 v) seg1 to seg35 (condition: v oh =v disp C1.5 v) (v) v fl voltage vs. output current of each driver
MSM9201-xx 32/34 ? semiconductor MSM9201-01 rom code 00000000b (00h) to 00001111b (0fh) are the cgram addresses. 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 ram0 ram1 ram2 ram3 ram4 ram5 ram6 ram7 msb lsb ram8 ram9 rama ramb ramc ramd rame ramf
MSM9201-xx 33/34 ? semiconductor (unit : mm) package dimensions notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.85 typ. qfp80-p-1414-0.65-k mirror finish
MSM9201-xx 34/34 ? semiconductor (unit : mm) notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). qfp80-p-1420-0.80-bk package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 1.27 typ. mirror finish

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